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Questions For high performance computing mcq
Q.l A pipeline is like
(A) An Automobile Assembly Line
(B) House Pipeline
(C) Both A And 8
(D) AGas Line
Q.2 Data hazards occur when
(A) Greater pcrfomwance loss
(B) Pipeline changes the order of read read/write access to opcrands
(C) Some finclioml unit is not fully pipclincd
(D) Machine size is linnled
Q.3 Systems that do not have parallel processing capabilities are
(A) SISD
(B) SIMD
(C) MIMD
(D) All of the aboxe
Q4 How does the number of transistors per chip increase according to Moore 's law?
(A) Quadmtically
(B) Lincarly
(C) Exponcmially
(D) Cubicly
Q.5 Parallel processing may occur
(A) In Ihc instruction stream
(B) In the data stream
(C) Bolh|a] and [B]
(D) None of Ihc abowc
Q.6 Execution of several activities at the same time.
(A) Processing
(B) Parallel processing
(C) Serial processing
(D) Multitasking
Q.7 Cache memory works on the principle of
(A) Locality ofdala
(B) Locality of reference
(C) Locality of memory
(D) Locality of reference & memory
Q.8 SIMD represents an organization that
(A) Refers to a computer system capable of processing several programs at the same time.
(B) Represents organization of single computer containing a control unit, processor unit and a memory unit
(C) Includes many processing units under the supervision of a common control unit
(D) None of the above
Q.9 A processor performing fetch or decoding of different instruction during the execution of another instruction is called
(A) Super-scaling
(B) Pipe-lining
(C) Parallel Computation
(D) None of these
Q.10 General MIMD configuration usually called
(A) a multiprocessor
(B) a vector processor
(C) array processor
(D) none of the above
Q.11 MIMD stands for
(A) Multiple instruction multiple data
(B) Multiple instruction memory data
(C) Memory instruction multiple data
(D) Multiple information memory data
Q.12 MIPS stands for:
(A) Memory Instruction Per Second
(B) Major Instruction Per Second
(C) Million Instruction Per Second
(D) Main Information Per Second
Q.13 VLIW stands for:
(A) Very Long Instruction Word
(B) Vector Large Instruction Word
(C) Very Large Integrated Word
(D) Very Low Integrated Word
Q.14 The major disadvantage of pipeline is:
(A) High cost individual dedicated
(B) Initial setup time
(C) If branch instruction is encountered the pipe has to be flushed
(D) All of the above
Q.15 A topology that involves Tokens.
(A) Star
(B) Ring
(C) Bus
(D) Daisy Chaining
Q. 16 Which mechanism performs an analysis on the code to determine which data items may become unsafe for caching, and they mark those items accordingly?
(A) Directory protocol
(B) Snoopy protocol
(C) Server based cache coherence
(D) Compiler based cache coherence
Q.17 How many processors can be organized in 5-dimensional binary hypercube system?
(A) 25
(B) 10
(C) 32
(D) 20
Q. 18 In a three-cube structure, node 101 cannot communicate directly with node?
(A) 1
(B) 11
(C) 100
(D) 111
Q.19 snoopy cache protocol are used in based system
(A) Bus
(B) Mesh
(C) Star
(D) hypercube
Q.20 superscalar architecture contains -- execution units for instruction execution
(A) Multiple
(B) Double
(C) Single
(D) None Of The Above
Q.21 Multipoint topology is
(A) Bus
(B) Star
(C) Mesh
(D) ring
Q.22 the number of switch requirement for a network with n input and n output is
(A) n
(B) n2
(C) n3
(D) 14
Q.23 have been developed specifically for pipelined systems.
(A) Utility software
(B) Speed up utilities
(C) Optimizing compilers
(D) None of the above
Q.24 Which of the following is a combination of several processors on a single chip?
(A) Multicore architecture
(B) RISC architecture
(C) CISC architecture
(D) Subword parallelism
Q.25 The important feature of the VLIW is .....
(A) ILP
(B) Cost effectiveness
(C) Performance
(D) None of the mentioned
Q.26 The parallel execution of operations in VLIW is done according to the schedule determined by .....
(A) sk scheduler
(B) Interpreter
(C) Encoder
(D) Compiler
Q.27 The VLIW processors are much simpler as they do not require of .....
(A) Computational register
(B) Complex logic circuits
(C) SSD slots
(D) Scheduling hardware
Q.28 The VLIW architecture follows ..... approach to achieve parallelism.
(A) MISD
(B) MIMD
(C) SISD
(D) SIMD
Q.29 How many switch points are there in crossbar switch network that connects 9 processors to 6 memory modules?
(A) 50
(B) 63
(C) 60
(D) 54
Q.30 Task dependency graph is ---
(A) Directed
(B) Undirected
(C) Directed Acyclic
(D) Undirected Acyclic
Q.31 In task dependency graph longest directed path between any pair of start and finish node is called as ----
(A) Total Work
(B) Critical Path
(C) Task Path
(D) Task Length
Q.32 which of the following is not a granularity type
(A) Course Grain
(B) Large Grain
(C) Medium Grain
(D) Fine Grain
Q.33 which of the following is a an example of data decomposition
(A) Matrix Multiplication
(B) Merge Sort
(C) Quick Sort
(D) 15 Puzzal
Q.34 which problems can be handled by recursive decomposition
(A) Backtracking
(B) Greedy Method
(C) Divide And Conquer Problem
(D) Branch And Bound
Q.35 In this decomposition problem decomposition goes hand in hand with its execution
(A) Data Decomposition
(B) Recursive Decomposition
(C) Explorative Decomposition
(D) Speculative Decomposition
Q.36 which of the following is not an example of explorative decomposition
(A) n queens problem
(B) quick sort
(C) 15 puzzal problem
(D) tic tac toe
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Q.37 Which of the following is not an application of topological sorting?
(A) Finding prerequisite of a task
(B) Finding Deadlock in an Operating System
(C) Ordered Statistics
(D) Finding Cycle in a graph
Q.38 In ------------task are defined before starting the execution of the algorithm
(A) Dynamic Task
(B) Static Task
(C) Regular Task
(D) One Way Task
Q.39 which of the following is not the array distribution method of data partitioning
(A) Block
(B) Cyclic
(C) Block Cyclic
(D) Chunk
Q.40 blocking optimization is used to improve temporal locality for reduce
(A) Misses
(B) Hit Miss
(C) Hit Rate
(D) Cache Misses
Q.41 threads being block altogether and being executed in the sets of 32 threads called a
(A) thread block
(B) 32 thread
(C) 32 block
(D) unit block
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